(1) Field of the Invention
The present invention relates generally to the field of logic synthesis for integrated circuit devices. More particularly, aspects of the present invention relate to methods and apparatus for design for test within a logic synthesis system.
(2) Background of the Related Art
Complex integrated circuits are designed with the use of computer aided design (CAD) tools. Specifically, application specific integrated circuits (ASICs) and field programmable gate array (FPGA) circuits can be designed using a variety of CAD tools. The development of ASICs and FPGA circuits with the aid of CAD tools is referred to as electronic design automatic or EDA. Design, checking and testing of large scale integrated circuits are so complex that the use of programmed computer systems are required for realization of normal circuits. This is partly because the integrated devices are inherently complex and partly because the circuit design needs to be decomposed into simpler functions which are recognized by the CAD tool. It is also partly because considerable computation is required in order to achieve an efficient layout of the resultant network. The result of the computerized design process is a detailed specification defining a complex integrated circuit in terms of a particular technology. This specification can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Integrated circuit designs can be represented in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. Two exemplary forms of HDL are Verilog and VHDL. The integrated circuit can be represented by different layers of abstractions (e.g., behavioral levels, structural levels and gate levels). An RTL level is an intermediary level of abstraction between the behavioral and structural levels. HDL descriptions can represent designs of all these levels.
The behavior levels and RTL levels consist general ly of descriptions of the circuit expressed with program-like constructs, such as variables, operators conditional loops, procedures and functions. At the logic level, the descriptions of the circuit are expressed with Boolean equations. The HDL can be used along with a set of circuit constraints as an input to a computer implemented compiler (also called a "silicon compiler"). The computer implemented compiler program processes this description of the integrated circuit and generates therefrom a detailed list of logic components and the interconnections between these components. This list is called a "netlist." The components of a netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches and D-flip flops, etc. and their interconnections used to form a custom design.
In processing the HDL input, the compiler first generates a netlist of generic primitive cells that are technology independent. The compiler then applies a particular cell library to this generic netlist (this process is called mapping) in order to generate a technology dependent mapped netlist. The mapping process converts the logical representation which is independent of technology into a form which is technology dependent. The mapped netlist has recourse to standard circuits, or cells which are available within a cell library forming a part of the data available to the computer system.
Compiler programs and mapping programs are well known in the art and several of these systems are described in U.S. Pat. No. 5,406,497, by Altheimer et al.
An important part of the logic synthesis process involves designing for testability. Programs that aid in the testability process of logic synthesis are called design for test (DFT) processes. As part of DFT, it is known to take the mapped netlist generated from a compiler and add and/or replace certain memory cells and associated circuitry with special memory cells that are designed to allow the application of test vectors to certain logic portions of the integrated circuit. The act of applying test vectors is called stimulation of the design and the special memory cells and associated circuitry are referred to as DFT implementations. Issues concerning controllability deal with facilitating the application of the test vectors to the circuitry to be tested. The same memory cells can be used to capture the output of the circuitry for observation and compare this output to the expected output in an effort to determine if circuit (e.g., manufacturing) defects are present.
The portions of an integrated circuit that are designed to perform its intended or expected operational function are called its "mission mode" circuitry while the portions added to the integrated circuit to facilitate testability are called "test mode" circuitry or DFT implementations. The resultant circuit therefore has two functional modes, mission and test.
An exemplary flow chart diagram of a typical logic synthesis process, including a DFT process, is shown in FIG. 1. The processes 200 described with respect to this flow chart is implemented within a computer system in a CAD environment. High level design language (HDL) descriptions of the integrated circuit enter at block 201. Also accompanying the HDL 201 is a set of performance constraints 205 applicable to the design which typically include timing, area, power consumption, and other performance related limitations that the compiler 225 will attempt to satisfy when synthesizing the integrated circuit design. Constraints 205 can also include non-performance related constraints such as structural and routing constraints. Compiler 225 consists of a generic compiler 203 (also called an HDL compiler, RTL synthesizer, or architectural optimizer) that inputs the HDL 201 description and generates therefrom a technology independent or "generic" netlist 207 which is also dependent on the constraints 205. As discussed above, the netlist 207 is a list of technology independent components or operators and the interconnections between there.
The generic netlist 207 is then input to a design compiler 209 that includes a computer implemented logic optimization procedure and a mapping procedure which interfaces with a technology dependent cell library 230 (e.g., from LSI, VLSI, TI or Xilinx technologies, etc.). The cell library 230 contains specific information regarding the cells of the specific technology selected such as the cell logic, number of gates, area consumption, power consumption, pin descriptions, etc., for each cell in the library 230. Logic optimization procedure of block 209 includes structuring and flattening procedures. The mapping procedure of block 209 generates a gate level mapped netlist 211 that is technology dependent having cells specifically selected to satisfy the constraints 205. This gate level netlist 211 consists at this point of "mission mode" circuitry.
At block 212 of FIG. 1, DFT process 213 performs a particular test insertion process (here a scan) to implement testability cells or "test mode" cells into the overall integrated circuit design. In this process 213, memory cells of the mapped netlist 211 are replaced with memory cells that are specially designed to apply and observe test vectors or patterns to and from portions of the integrated circuit. In one particular DFT process, these memory cells specially designed for test are called scannable memory cells. The test vector patterns can be derived from combinational or sequential automatic test pattern generation (ATPG) processes depending on whether or not a full or partial scan is performed by the scan insertion process 213. Process 213 also performs linking groups of scannable memory cells into scan chains so that the test vectors can be cycled into and out of the integrated circuit design. The output of the scan insertion process 213 is a scannable netlist 215 that contain., both mission and test mode circuitry.
A problem occurs in the prior art process of FIG. 1 in that the scan insertion process 213 does not take into account its impact on the mission mode design. Specifically, the addition of the testability cells (scannable cells), and interconnections there between (chaining resources), and the addition of other dedicated connections required for operation of the scan chains (e.g., scan clock routing and scan enable signal routing) can cause the overall design to violate one or more of the defined constraints 205.
Therefore, a second compile process 217 of FIG. 1 (full or incremental compile) is invoked by the prior art process 200 in order to more effectively optimize the scannable netlist 215 to the constraints 205. An incremental compile 217 does not process all existing structure as in a full compile, it only applies high level logical optimization to the unmapped portions of the design. Those unmapped portions are then mapped using a technology dependent library. During a process iteration, an incremental compile 217 always processes to decrease the circuit cost. However, although this second compile process 217 is only an incremental compile process, it applies mapping optimizations iteratively on the entire scannable netlist 215. As a result, processing time to perform the second compile process 217 can be on the order of weeks given conventional CAD technology and circuit complexity.
Alternatively, many prior systems utilize a full compile as the second compile process 217. The full compile process is similar to process 225 in that the full compile process at 217 applies mapping and logic optimizations to the entire design, not just the unmapped portions.
After the second compile process 217 of FIG. 1 completes, a scannable netlist 219 is again generated that contains the testability cells but that may or may not meet the original performance constraints 205. Therefore, at block 221, the prior art then performs a test to determine if the scannable netlist 219 meets the constraints 205. If the netlist 219 meets the constraints, then at block 235, other circuit synthesis procedures, continue until the integrated circuit design can be fabricated onto a substrate and tested.
However, as is often the case, the addition of the testability cells by the scan insertion process 213 does not allow the second compile process 217 to meet constraints 205 without a design modification to the original HDL program 201. In such case, the overall process 200 flows from block 221 back to the HDL 201 where the architect modifies the HDL program 201 so that the addition of the testability cells and other resources will eventually satisfy, when possible, the given constraints 205 after the incremental compile step 217 is again executed.
The prior art process 200 of FIG. 1 has several disadvantages. It is disadvantageous to execute a second substantial compile process 217 in an attempt to match the testability cells and linking resources to the given set of constraints. Although this process can be an incremental compile step in that much of the gate level connections are not removed, mapping optimization portions of this compile process still operate in an iterative fashion over the entire design. The addition of this second compile process, using conventional technology, delays the overall integrated circuit synthesis process by as much as one to two weeks. Even after this long delay, there are no guarantees that the incremental compile process 217 will generate a scannable netlist satisfying the constraints 205. In this case, a time consuming task of returning to the HDL for redesign is required. This process involves the chip architect designers once more and, therefore, it is unclear under the prior art system when a designer can sign off on his or her work in the design process.
Another problem faced by prior art designs involving the introduction of scan cells for testability while maintaining optimization constraints (e.g., timing and area constraints) is that the timing and area constraints cannot be met in some designs if the entire design is scan replaced. This is true no matter how many conventional compile processes are executed after the scan insertion block. Therefore, it would be desirable to determine a set of sequential cells that can be scan replaced to just meet the timing and area constraints while offering significant testability for the design. What is needed is a system that effectively determines a set of sequential cells within a design that can be scan replaced while satisfying given timing and area constraints of the design. The present invention provides this functionality. Further, what is needed is a system that can perform the above based on iterations through determined critical paths of the design. The present invention additionally provides this functionality.
Accordingly, the present invention advantageously provides a system for effectively determining the amount of sequential cells within a design that can be scan replaced while satisfying given timing and area constraints of the design and still offering significant testability for the design. It is an object of the present invention to provide the above within a selected set of scan cells that attempts to offer a high degree of testability given the timing and area constraints to be satisfied. It is an object of the present invention to provide a subtractive system for performing the above wherein a fully scan replaced netlist (that violates timing and area constraints) is input and selected cells are unscanned until the timing and area constraints are met. It is another object of the present invention to provide an additive system wherein an unscanned netlist is received, and using a cell based or a critical path based system, cells are scanned that do not make the timing of the original system any worse than originally submitted until a significant number of sequential cells are scan replaced or area constraints are violated. These and other objects of the present invention not specifically recited above will become clear within discussion of the present invention herein.